Make

make is an automation tools help you run and compile program more efficiently. make need a special file Makefile in your working directory, which defines a set of tasks for automation.

A basie example of make file is as following. You can use make command to print a ‘hi’ in the console.

say_hi:
	echo "hi"

This example contains only one task, each task has a structure like:

target: prerequisties
<TAB> recipe

Remember to use tab instead of 4 spaces in Makefile.

target: prerequisties
<TAB> command1
<TAB> -commend1  # ignore errors
<TAB> @comand3  # suppress echoing
Automatic Variable Value
$@ target
$< first prerequisite
$? all newer prerequisities
$^ all prerequisities
$* ”%” matched item in the target pattern
Variable Expansion Description
foo1 := bar one-time expansion
foo2 = bar recursive expansion
foo3 += bar append

Run make -p -f /dev/null to see automatic internal rules.

# Usage:
# make        # compile all binary
# make clean  # remove ALL binaries and objects

.PHONY = all clean

CC = gcc                        # compiler to use

LINKERFLAG = -lm

SRCS := foo.c
BINS := foo

all: foo

foo: foo.o
        @echo "Checking.."
        gcc -lm foo.o -o foo

foo.o: foo.c
        @echo "Creating object.."
        gcc -c foo.c

clean:
        @echo "Cleaning up..."
        rm -rvf foo.o foo

参考资料

CMake

cmake_minimum_required(VERSION 3.10)

# set the project name
project(Tutorial)

# add the executable
add_executable(Tutorial tutorial.cxx)

参考资料